SK Hynix Stock & HBM Evolution: Standards, Stack Architecture & the AI Capacity Bottleneck

Focus companies in this thesis (1)

• SK Hynix Inc. (000660.KS)

Supply-chain categories covered

• HBM — High Bandwidth Memory — 3D-stacked DRAM (HBM2E/HBM3/HBM3E/HBM4) connected via through-silicon vias, delivering 1+ TB/s of bandwidth per stack. Co-packaged with GPUs, TPUs, and custom AI accelerators for datacenter AI training/inference and HPC workloads.
• DRAM — Dynamic random-access memory chips
• Through-Silicon Via (TSV) Process — Through-Silicon Via (TSV) is the vertical copper interconnect that passes through silicon dies to enable 3D stacking — the foundational technology that makes HBM physically possible. The full TSV process flow adds ~19 materials-engineering steps on top of the ~700 steps for standard DRAM and spans deep silicon etching, oxide liner deposition, barrier and seed layer PVD, electrochemical copper fill, CMP, wafer thinning, and double-sided processing. Equipment-side concentrated at Applied Materials (TSV etch + drill-and-fill, ~75% process-step coverage), Lam Research (deep silicon etch, multi-year SK hynix deal), and Tokyo Electron. The wafer-thinning and dicing duopoly sits with Disco and Tokyo Seimitsu/Accretech.
• TCB Equipment — Thermo-compression bonding equipment for advanced packaging including HBM stacking.
• Hybrid Bonding Equipment — Direct copper-to-copper bonding without solder microbumps — the next-generation stacking interconnect for HBM5+ and high-end logic-on-logic 3D integration. Enables sub-1µm pitches versus 25-40µm for thermocompression bonding (TCB), allowing 20-Hi+ HBM stacks and TSMC SoIC. Wafer-to-wafer (W2W) hybrid bonding is expected to become mainstream in the HBM5 generation (~2028-2029); die-to-wafer (D2W) for higher mix. Equipment is concentrated at BE Semiconductor (BESI), ASMPT, and Applied Materials, with EV Group and SUSS Microtec on the prep side.
• CoWoS / 2.5D-3D Integration — TSMC's CoWoS (Chip-on-Wafer-on-Substrate) family and equivalents — the 2.5D and 3D packaging platforms that integrate logic dies with HBM stacks on a silicon or RDL interposer. Includes CoWoS-S, CoWoS-R, CoWoS-L (Local Silicon Interconnect with embedded bridges), and SoIC (System on Integrated Chips) 3D stacking. The binding capacity bottleneck for every leading-edge AI accelerator from NVIDIA H100/Blackwell/Rubin through AMD MI300/MI400 and hyperscaler custom silicon.
• Foundry / Fab Services — Contract semiconductor manufacturing — wafer fabrication for fabless and partially-fabless customers, spanning leading-edge logic, mature-node analog/mixed-signal, RF, and specialty processes (BCD, BiCMOS, SiC, SOI).
• Wafer Inspection & Metrology — Defect inspection, CD-SEM, overlay measurement tools
• Probe Cards & Test Sockets — Wafer probe cards and IC test sockets
• Specialty Gases & Chemicals — Ultrapure gases, CMP slurries, and process chemicals.
• Glass Substrates — Glass substrates and glass-core packaging — the post-organic-substrate path for HBM4/HBM5-class advanced packaging. Glass offers flatter surfaces, superior dimensional stability, lower CTE mismatch, and finer through-glass via (TGV) pitches than ABF organic substrates, all of which become essential at 14+ reticle-size interposers carrying 24 HBM5E stacks (TSMC 2029 roadmap). Pilot ramps are happening through 2026-2028 at Ibiden, Unimicron, Hoya (substrate blanks), and Samsung. Intel announced glass-core substrates for second-half 2020s; AMD and TSMC are co-developing with substrate partners.
• AI GPUs — Compute accelerators and GPUs powering AI training, inference, and large language models.

Thesis milestones & bottleneck markers

• SK hynix revenue ≥ ₩100T (HBM mix proves out) — 000660.KS — SK hynix annual revenue passes ₩100 trillion driven by HBM3E and HBM4 mix. FY24 baseline ~₩66T; HBM as % of total DRAM revenue scaling from ~20% to >40%. HBM demand +77% YoY per TrendForce. SK hynix at ₩1,779,000 (-7.3% today ahead of Q2 earnings July 28). Q2 report is pivotal — HBM4 revenue commentary will directly test whether FY26 is on track for ₩100T.
• Micron revenue ≥ $50B (HBM3E + HBM4 ramp) — MU — Micron FY26 revenue exceeds $50B as HBM3E volumes hit and HBM4 begins to contribute. FY25 baseline ~$37B. MU at $987.29 (+2.9% today) — bucking the memory sell-off on Google cloud optimism and Tesla allocation confirmation. MU is the only major memory stock positive today, suggesting HBM demand narrative remains intact for non-Korean suppliers.
• Samsung Electronics revenue ≥ ₩320T (HBM4 qualification) — BINARY ON JUL 29 — 005930.KS — Samsung Electronics consolidated revenue passes ₩320T — implies HBM4 share recovery at NVIDIA and continued strength in memory + foundry. Samsung at ₩249,250 (-7.7% today in sharp sell-off ahead of July 29 earnings). Market pricing suggests skepticism on HBM4 qualification progress at NVIDIA. Q2 earnings on July 29 are a binary catalyst — either confirms HBM4 qualification and revenue is on track, or the milestone becomes at-risk.
• TSMC market cap ≥ $1.5T (CoWoS + base-die capture) — TSM — TSMC market cap passed $1.5T reflecting CoWoS oligopoly and HBM4E custom base-die wins. ACHIEVED. TSM at $414.90 (-1.5% today). Note: NVIDIA-Amkor $1.5B packaging deal adds a second-source to CoWoS, but TSMC remains the dominant advanced packaging provider with ~130-150kwpm CoWoS-L capacity. Base-die foundry role for HBM4E is incremental to this milestone.
• NVIDIA market cap ≥ $5T (sustained Rubin demand) — NVDA — NVIDIA market cap passed $5T, signaling sustained AI accelerator demand and HBM-content monetization. ACHIEVED. NVDA at $212.50 (+0.3% today, -4.4% since inception) — NVDA resilient amid today's memory sell-off, confirming the market distinguishes between HBM IDM dilution risk and AI compute demand. Rubin ramp remains the next catalyst; earnings Aug 26.
• SK hynix market cap ≥ $1T — 000660.KS — SK hynix market cap crossed $1T briefly on May 26, 2026, then fell back during the record -15% single-day crash. As of July 24, ₩1,779,000 (-7.3% today in broad semiconductor sell-off) — significantly below $1T threshold. KRW/USD at ~1,400 means roughly ₩1,400,000 per $1B market cap — needs approximately ₩1,400,000+ share price. Today's price implies market cap ~$950-970B. Q2 earnings on July 28 are the next catalyst.
• KLIC EPS ≥ $4 (TCB volume + HBM design-in) — KLIC — Kulicke & Soffa annual EPS exceeds $4, indicating TCB revenue converting from <$100M guide to a multi-hundred-million-dollar business. KLIC at $97.22 (-1.8% today) — relatively resilient in today's selloff. TCB tooling demand tied to HBM4 capacity expansion. Earnings Aug 6 will provide next checkpoint. KLIC's TCB momentum is a leading indicator for the HBM4 equipment cycle.
• Micron market cap ≥ $1T — Micron Technology market cap surpassed $1T in May 2026 but has fallen back. MU currently at $987.29 (+2.9% today). Market cap flirting with $1T threshold again. Google cloud spending and Tesla memory allocation provide demand tailwinds. HBM3E ramp and HBM4 qualification remain catalysts.
• Disco revenue ≥ ¥500B (TSV wafer-thinning monopoly) — 6146.T — Disco annual revenue exceeds ¥500B reflecting structural demand from every HBM and CoWoS wafer requiring thinning and dicing. Disco at ¥60,080 (-13.4% today in sharp equipment sell-off). Sharp correction raises near-term concern but structural demand for wafer thinning/dicing remains intact — every HBM stack requires Disco tools. FY ending March 2027 target.
• Advantest revenue ≥ ¥1T (memory ATE supercycle) — 6857.T — Advantest revenue exceeds ¥1T driven by HBM test capacity expansion and SoC ATE for AI accelerators. Advantest at ¥29,080 (+5.7% today) — strong bounce from prior selloff. Earnings July 29 alongside Samsung. Memory ATE supercycle thesis intact; demand for HBM4 final test is structurally rising.

Related baskets

• Memory Supercycle
• HBM / Packaging
• Lithography & Fab Tools
• Custom Silicon
• Networking / Retimers

More AI supply-chain theses

• Grid, transmission, utility-scale power integration
• Vicor Stock (VICR): Last-Inch Power Delivery to AI GPUs
• Custom-silicon duopoly with AVGO
• SOI substrate monopoly for silicon photonics engines
• Hybrid-bonding integrated tool jointly with BESI
• Comfort Systems (FIX) — MEP/HVAC contractor riding the AI data center super-cycle
• Photonics & Datacenter Buildout: Supply-Chain Impact (SIVERS)
• THE optical contract manufacturer
• Only US rare-earth producer at scale
• Kulicke & Soffa (KLIC) — Strait of HBM TCB
• WaveLogic 6 Extreme 1
• EUV monopoly

Frequently asked questions

What is the SK Hynix Stock & HBM Evolution: Standards, Stack Architecture & the AI Capacity Bottleneck thesis about?

**Bottleneck theme:** Memory / Advanced Packaging **Focus:** $000660.KS — SK hynix Inc. SK Hynix stock ($000660.KS) is the HBM bellwether — High-Bandwidth Memory is the second moat under AI compute. Every leading-edge AI accelerator — NVIDIA Blackwell/Rubin, AMD MI355/MI400, Broadcom and Marvell custom silicon, Google TPU, AWS Trainium — depends on 8 to 16 stacks of HBM3E/HBM4 co-packaged on a CoWoS interposer. HBM is supply-constrained, structurally tight through 2027, and the standards roadmap is accelerating, not slowing. HBM4 doubles the interface from 1024 to 2048 bits, marking the first architectural break since the standard was created in 2013. HBM4E and HBM5 introduce a "customized HBM" model where the logic base die is fabbed on a leading-edge foundry node, pulling TSMC and Samsung Foundry into the HBM bill of materials. ## How to play it Three layers of exposure: 1. **HBM IDMs** (SK hynix, Micron, Samsung) — direct beneficiaries of unit + ASP + content growth; the SK hynix–TSMC partnership for custom HBM4E base dies is the strongest competitive position. 2. **Packaging equipment** through each architectural transition: TCB (KLIC, ASMPT) → hybrid bonding (BESI, ASMPT, AMAT) → dicing/grinding/CMP (Disco, Accretech) → inspection (Lasertec, ONTO, CAMT) → probe & test (FORM, Advantest, Teradyne). 3. **Foundry & substrate** capture from HBM4E onward: TSMC's CoWoS-L and SoIC capacity, base-die wafer starts at TSMC/Samsung Foundry, glass substrate ramp at Ibiden/Unimicron, and the silicon/copper/fluid materials (Entegris, Shin-Etsu, Resonac). ## The standards roadmap (architectural transitions) | Generation | Spec / Mass-prod year | Pin speed | Interface | Bandwidth/stack | Max Hi | GB/stack | Key inflection | |---|---|---|---|---|---|---|---| | HBM1 | 2013 / 2015 | 1.0 Gbps | 1024-b | 128 GB/s | 4-Hi | 1 GB | First TSV-stacked DRAM (AMD Fiji) | | HBM2 | 2016 / 2018 | 2.4 Gbps | 1024-b | 256 GB/s | 4–8-Hi | 8 GB | NVIDIA P100/V100 ramp | | HBM2E | 2018 / 2020 | 3.6 Gbps | 1024-b | ~460 GB/s | 8-Hi | 16 GB | A100 socket | | HBM3 | Jan 2022 / 2022 | 6.4 Gbps | 1024-b | ~819 GB/s | 12-Hi | 24 GB | H100; channel re-architecture | | HBM3E | May 2023 / 2024 | 9.6 Gbps | 1024-b | ~1.2 TB/s | 12–16-Hi | 24–36 GB | H200, B100/B200/B300, MI300X/MI355 | | **HBM4** | Apr 2025 / 2026 | 6.4 GT/s baseline (custom > 11 Gbps) | **2048-b** | **>2 TB/s** | 16-Hi | 36–64 GB | Wider bus; **logic base die**; Rubin / MI400 | | **HBM4E** | 2027 | ~9 GT/s | 2048-b | ~3 TB/s+ | 8–16-Hi | up to ~64 GB+ | **Customized base die** fabbed at TSMC/Samsung Foundry; ~40% of HBM market by 2027 | | **HBM5 / HBM5E** | 2029–2031 | TBD | 2048-b+ | ~4 TB/s+ | 20-Hi | TBD | Wafer-to-wafer hybrid bonding mainstream; immersion cooling; 14-reticle CoWoS interposers carrying up to 24 HBM5E stacks | Bandwidth growth is **accelerating**, not slowing. HBM1 → HBM3E (a decade) was roughly a 10× bandwidth increase via pin-speed scaling on a fixed 1024-bit bus. HBM4 alone delivers ~2× over HBM3E in one generation by doubling the interface to 2048 bits — the first architectural break since the standard was created. Capacity per stack has 36×'d (1 GB HBM1 → 36 GB HBM3E → 64 GB HBM4 16-Hi). NVIDIA's roadmap shows HBM capacity per accelerator going from 80 GB (A100, HBM2E) to ~1,024 GB (Rubin Ultra, HBM4E) — a 12.8× system-level capacity increase across five GPU generations. ## The big architectural pivot: customized HBM (HBM4E+) Starting with HBM4E, the base die under the DRAM stack becomes customer-specific. The HBM controller and protocol logic move from the GPU/ASIC onto the HBM base die itself, freeing up compute silicon area on the accelerator. The base die now needs to be fabbed on an advanced logic node — which is why **SK hynix is partnering with TSMC on base dies for custom HBM4E and HBM5**, and why **Samsung is using its own foundry process for the HBM4 logic die** as a vertical-integration play. Micron is the question mark: no captive foundry, but targeting custom HBM4E in 2027 with claims of higher margins. This is the single most important industry shift in HBM since stacking itself — it widens the moat for whoever can pair memory expertise with leading-edge foundry access. ## What we're watching (horizons) - **2026 (live):** HBM4 12-Hi ramp at SK hynix and Micron; NVIDIA Rubin TS1 silicon; CoWoS-L capacity reaching ~130–150kwpm at TSMC; Samsung re-qualification at NVIDIA for HBM4; HBM demand +77% YoY (TrendForce). - **2026–2027:** Custom HBM4E base-die qualification (SK hynix↔TSMC, Samsung integrated); TCB→hybrid-bonding transition decision at lead HBM lines; HBF (high-bandwidth flash) sampling at Kioxia/Sandisk/Micron. - **2027–2028:** HBM4E commercial volume (~40% of HBM market by 2027); glass-substrate pilot ramp at Ibiden/Unimicron; W2W hybrid bonding qualification; HBM demand +68% YoY. - **2029–2031:** HBM5/HBM5E development; 20-Hi stacks mainstream; 14-reticle CoWoS interposers carrying 24 HBM5E stacks; immersion-cooling integration; HBM TAM moving past $80B. ## Key bottlenecks and pinch points - **CoWoS-L capacity at TSMC** (currently the binding constraint, not HBM die supply) — NVIDIA holds ~60% of TSMC's CoWoS allocation through 2026. - **TCB tooling and the TCB→hybrid bonding transition** — KLIC and ASMPT in TCB; BESI + ASMPT + AMAT in hybrid bonding. - **Wafer thinning / dicing** — Disco–Accretech duopoly; mandatory for every TSV-bearing wafer. - **Memory ATE** — Advantest near-monopoly on HBM final test, Teradyne gaining share. - **Probe cards** — FormFactor; every HBM die is wafer-tested. - **Specialty chemicals & gases** — Entegris, Shin-Etsu, Resonac, Tokyo Ohka, Linde, Air Products. - **Substrates** — Ibiden, Unimicron, Hoya transitioning ABF organic → glass.

Which companies does the SK Hynix Stock & HBM Evolution: Standards, Stack Architecture & the AI Capacity Bottleneck thesis focus on?

The SK Hynix Stock & HBM Evolution: Standards, Stack Architecture & the AI Capacity Bottleneck thesis on Macroplane focuses on SK Hynix Inc. (000660.KS).

Which supply-chain categories does the SK Hynix Stock & HBM Evolution: Standards, Stack Architecture & the AI Capacity Bottleneck thesis cover?

It covers HBM, DRAM, Through-Silicon Via (TSV) Process, TCB Equipment, Hybrid Bonding Equipment, CoWoS / 2.5D-3D Integration, Foundry / Fab Services, Wafer Inspection & Metrology, Probe Cards & Test Sockets, Specialty Gases & Chemicals, and 2 more.