SK Hynix Stock & HBM Evolution: Standards, Stack Architecture & the AI Capacity Bottleneck
AI supply-chain thesis — mapping bottlenecks, focus companies, and supply-chain exposure for investors.
**Bottleneck theme:** Memory / Advanced Packaging
**Focus:** $000660.KS — SK hynix Inc.
SK Hynix stock ($000660.KS) is the HBM bellwether — High-Bandwidth Memory is the second moat under AI compute. Every leading-edge AI accelerator — NVIDIA Blackwell/Rubin, AMD MI355/MI400, Broadcom and Marvell custom silicon, Google TPU, AWS Trainium — depends on 8 to 16 stacks of HBM3E/HBM4 co-packaged on a CoWoS interposer. HBM is supply-constrained, structurally tight through 2027, and the standards roadmap is accelerating, not slowing. HBM4 doubles the interface from 1024 to 2048 bits, marking the first architectural break since the standard was created in 2013. HBM4E and HBM5 introduce a "customized HBM" model where the logic base die is fabbed on a leading-edge foundry node, pulling TSMC and Samsung Foundry into the HBM bill of materials.
## How to play it
Three layers of exposure:
1. **HBM IDMs** (SK hynix, Micron, Samsung) — direct beneficiaries of unit + ASP + content growth; the SK hynix–TSMC partnership for custom HBM4E base dies is the strongest competitive position.
2. **Packaging equipment** through each architectural transition: TCB (KLIC, ASMPT) → hybrid bonding (BESI, ASMPT, AMAT) → dicing/grinding/CMP (Disco, Accretech) → inspection (Lasertec, ONTO, CAMT) → probe & test (FORM, Advantest, Teradyne).
3. **Foundry & substrate** capture from HBM4E onward: TSMC's CoWoS-L and SoIC capacity, base-die wafer starts at TSMC/Samsung Foundry, glass substrate ramp at Ibiden/Unimicron, and the silicon/copper/fluid materials (Entegris, Shin-Etsu, Resonac).
## The standards roadmap (architectural transitions)
| Generation | Spec / Mass-prod year | Pin speed | Interface | Bandwidth/stack | Max Hi | GB/stack | Key inflection |
|---|---|---|---|---|---|---|---|
| HBM1 | 2013 / 2015 | 1.0 Gbps | 1024-b | 128 GB/s | 4-Hi | 1 GB | First TSV-stacked DRAM (AMD Fiji) |
| HBM2 | 2016 / 2018 | 2.4 Gbps | 1024-b | 256 GB/s | 4–8-Hi | 8 GB | NVIDIA P100/V100 ramp |
| HBM2E | 2018 / 2020 | 3.6 Gbps | 1024-b | ~460 GB/s | 8-Hi | 16 GB | A100 socket |
| HBM3 | Jan 2022 / 2022 | 6.4 Gbps | 1024-b | ~819 GB/s | 12-Hi | 24 GB | H100; channel re-architecture |
| HBM3E | May 2023 / 2024 | 9.6 Gbps | 1024-b | ~1.2 TB/s | 12–16-Hi | 24–36 GB | H200, B100/B200/B300, MI300X/MI355 |
| **HBM4** | Apr 2025 / 2026 | 6.4 GT/s baseline (custom > 11 Gbps) | **2048-b** | **>2 TB/s** | 16-Hi | 36–64 GB | Wider bus; **logic base die**; Rubin / MI400 |
| **HBM4E** | 2027 | ~9 GT/s | 2048-b | ~3 TB/s+ | 8–16-Hi | up to ~64 GB+ | **Customized base die** fabbed at TSMC/Samsung Foundry; ~40% of HBM market by 2027 |
| **HBM5 / HBM5E** | 2029–2031 | TBD | 2048-b+ | ~4 TB/s+ | 20-Hi | TBD | Wafer-to-wafer hybrid bonding mainstream; immersion cooling; 14-reticle CoWoS interposers carrying up to 24 HBM5E stacks |
Bandwidth growth is **accelerating**, not slowing. HBM1 → HBM3E (a decade) was roughly a 10× bandwidth increase via pin-speed scaling on a fixed 1024-bit bus. HBM4 alone delivers ~2× over HBM3E in one generation by doubling the interface to 2048 bits — the first architectural break since the standard was created. Capacity per stack has 36×'d (1 GB HBM1 → 36 GB HBM3E → 64 GB HBM4 16-Hi). NVIDIA's roadmap shows HBM capacity per accelerator going from 80 GB (A100, HBM2E) to ~1,024 GB (Rubin Ultra, HBM4E) — a 12.8× system-level capacity increase across five GPU generations.
## The big architectural pivot: customized HBM (HBM4E+)
Starting with HBM4E, the base die under the DRAM stack becomes customer-specific. The HBM controller and protocol logic move from the GPU/ASIC onto the HBM base die itself, freeing up compute silicon area on the accelerator. The base die now needs to be fabbed on an advanced logic node — which is why **SK hynix is partnering with TSMC on base dies for custom HBM4E and HBM5**, and why **Samsung is using its own foundry process for the HBM4 logic die** as a vertical-integration play. Micron is the question mark: no captive foundry, but targeting custom HBM4E in 2027 with claims of higher margins.
This is the single most important industry shift in HBM since stacking itself — it widens the moat for whoever can pair memory expertise with leading-edge foundry access.
## What we're watching (horizons)
- **2026 (live):** HBM4 12-Hi ramp at SK hynix and Micron; NVIDIA Rubin TS1 silicon; CoWoS-L capacity reaching ~130–150kwpm at TSMC; Samsung re-qualification at NVIDIA for HBM4; HBM demand +77% YoY (TrendForce).
- **2026–2027:** Custom HBM4E base-die qualification (SK hynix↔TSMC, Samsung integrated); TCB→hybrid-bonding transition decision at lead HBM lines; HBF (high-bandwidth flash) sampling at Kioxia/Sandisk/Micron.
- **2027–2028:** HBM4E commercial volume (~40% of HBM market by 2027); glass-substrate pilot ramp at Ibiden/Unimicron; W2W hybrid bonding qualification; HBM demand +68% YoY.
- **2029–2031:** HBM5/HBM5E development; 20-Hi stacks mainstream; 14-reticle CoWoS interposers carrying 24 HBM5E stacks; immersion-cooling integration; HBM TAM moving past $80B.
## Key bottlenecks and pinch points
- **CoWoS-L capacity at TSMC** (currently the binding constraint, not HBM die supply) — NVIDIA holds ~60% of TSMC's CoWoS allocation through 2026.
- **TCB tooling and the TCB→hybrid bonding transition** — KLIC and ASMPT in TCB; BESI + ASMPT + AMAT in hybrid bonding.
- **Wafer thinning / dicing** — Disco–Accretech duopoly; mandatory for every TSV-bearing wafer.
- **Memory ATE** — Advantest near-monopoly on HBM final test, Teradyne gaining share.
- **Probe cards** — FormFactor; every HBM die is wafer-tested.
- **Specialty chemicals & gases** — Entegris, Shin-Etsu, Resonac, Tokyo Ohka, Linde, Air Products.
- **Substrates** — Ibiden, Unimicron, Hoya transitioning ABF organic → glass.
HBM — High Bandwidth Memory — 3D-stacked DRAM (HBM2E/HBM3/HBM3E/HBM4) connected via through-silicon vias, delivering 1+ TB/s of bandwidth per stack. Co-packaged with GPUs, TPUs, and custom AI accelerators for datacenter AI training/inference and HPC workloads.
Through-Silicon Via (TSV) Process — Through-Silicon Via (TSV) is the vertical copper interconnect that passes through silicon dies to enable 3D stacking — the foundational technology that makes HBM physically possible. The full TSV process flow adds ~19 materials-engineering steps on top of the ~700 steps for standard DRAM and spans deep silicon etching, oxide liner deposition, barrier and seed layer PVD, electrochemical copper fill, CMP, wafer thinning, and double-sided processing. Equipment-side concentrated at Applied Materials (TSV etch + drill-and-fill, ~75% process-step coverage), Lam Research (deep silicon etch, multi-year SK hynix deal), and Tokyo Electron. The wafer-thinning and dicing duopoly sits with Disco and Tokyo Seimitsu/Accretech.
TCB Equipment — Thermo-compression bonding equipment for advanced packaging including HBM stacking.
Hybrid Bonding Equipment — Direct copper-to-copper bonding without solder microbumps — the next-generation stacking interconnect for HBM5+ and high-end logic-on-logic 3D integration. Enables sub-1µm pitches versus 25-40µm for thermocompression bonding (TCB), allowing 20-Hi+ HBM stacks and TSMC SoIC. Wafer-to-wafer (W2W) hybrid bonding is expected to become mainstream in the HBM5 generation (~2028-2029); die-to-wafer (D2W) for higher mix. Equipment is concentrated at BE Semiconductor (BESI), ASMPT, and Applied Materials, with EV Group and SUSS Microtec on the prep side.
CoWoS / 2.5D-3D Integration — TSMC's CoWoS (Chip-on-Wafer-on-Substrate) family and equivalents — the 2.5D and 3D packaging platforms that integrate logic dies with HBM stacks on a silicon or RDL interposer. Includes CoWoS-S, CoWoS-R, CoWoS-L (Local Silicon Interconnect with embedded bridges), and SoIC (System on Integrated Chips) 3D stacking. The binding capacity bottleneck for every leading-edge AI accelerator from NVIDIA H100/Blackwell/Rubin through AMD MI300/MI400 and hyperscaler custom silicon.
Foundry / Fab Services — Contract semiconductor manufacturing — wafer fabrication for fabless and partially-fabless customers, spanning leading-edge logic, mature-node analog/mixed-signal, RF, and specialty processes (BCD, BiCMOS, SiC, SOI).
Glass Substrates — Glass substrates and glass-core packaging — the post-organic-substrate path for HBM4/HBM5-class advanced packaging. Glass offers flatter surfaces, superior dimensional stability, lower CTE mismatch, and finer through-glass via (TGV) pitches than ABF organic substrates, all of which become essential at 14+ reticle-size interposers carrying 24 HBM5E stacks (TSMC 2029 roadmap). Pilot ramps are happening through 2026-2028 at Ibiden, Unimicron, Hoya (substrate blanks), and Samsung. Intel announced glass-core substrates for second-half 2020s; AMD and TSMC are co-developing with substrate partners.
AI GPUs — Compute accelerators and GPUs powering AI training, inference, and large language models.
Thesis milestones & bottleneck markers
SK hynix revenue ≥ ₩100T (HBM mix proves out) — 000660.KS — SK hynix annual revenue passes ₩100 trillion driven by HBM3E and HBM4 mix. FY24 baseline was ~₩66T; HBM as % of total memory revenue scaling from ~20% to >40% should drive this. ON TRACK: SK hynix at KRW 2,116,000 (+15% since thesis inception). HBM4 12-Hi ramp underway; NVIDIA multi-year design partnership locked through HBM4E→HBM5. KRW 2,116,000 price shows market differentiation from commodity DRAM names. Key risk: Korean fund concentration overhang and Kospi macro pressure limiting upside despite fundamentals.
Micron revenue ≥ $50B (HBM3E + HBM4 ramp) — MU — Micron FY26 revenue exceeds $50B as HBM3E volumes hit and HBM4 begins to contribute. FY25 was ~$37B; HBM ASP/mix is the swing factor. CRITICAL: MU at $955 (+10.5% today, +40.1% since inception). June 24 earnings in 15 days — HBM4 margin guidance and custom HBM4E roadmap are the key catalysts. Today's +10.5% bounce suggests the market is positioning ahead of what could be the most important HBM earnings print of 2026. MU market cap already crossed $1T milestone (achieved).
Samsung Electronics revenue ≥ ₩320T (HBM4 qualification) — 005930.KS — Samsung Electronics consolidated revenue passes ₩320T — implies HBM4 share recovery at NVIDIA and continued strength in memory + foundry. AT RISK: SK hynix-NVIDIA multi-year design partnership announcement structurally weakens Samsung's HBM position. HBM4 qualification at NVIDIA remains uncertain. Samsung at KRW 311,000 (+10.7% since inception) underperforms SK hynix (+15%). If HBM4 qualification fails or is delayed, this milestone becomes unlikely.
NVIDIA market cap ≥ $5T (sustained Rubin demand) — NVDA — NVIDIA market cap passes $5T, signaling sustained AI accelerator demand and HBM-content monetization through Rubin and Rubin Ultra generations. ACHIEVED: NVDA is the world's most valuable company. CAUTION: NVDA -3.6% since inception, -0.5% today — market cap milestone met but price has pulled back, suggesting some air coming out of the multiple. Rubin ramp remains critical for sustaining above $5T.
SK hynix market cap ≥ $1T — 000660.KS — SK hynix market cap crosses $1 trillion, reflecting the market's structural re-rating of HBM-exposed memory names away from commodity DRAM cycles toward AI infrastructure premiums. ACHIEVED May 26, 2026 alongside MU's $1T crossing — the definitive signal that the HBM IDM thesis is being validated.
KLIC EPS ≥ $4 (TCB volume + HBM design-in) — KLIC — Kulicke & Soffa annual EPS exceeds $4, indicating TCB revenue converting from <$100M guide to a multi-hundred-million-dollar business plus continued wire-bond cash flow. MONITOR: KLIC at $103 (+4.9% today, +3.7% since inception). TCB tooling demand structurally tied to HBM4 ramp. KLIC and ASMPT are the incumbent TCB suppliers; HBM4's 16-Hi stacks increase TCB attach count per stack. Key risk: TCB→hybrid bonding transition timeline could compress KLIC's TCB runway.
Micron market cap ≥ $1T — Micron Technology market cap crosses $1 trillion, driven by HBM3E volume ramp, HBM4 qualification progress, and "enhanced long-term agreements" with AI customers. ACHIEVED May 26, 2026 alongside SK hynix's $1T crossing — both HBM IDMs re-rated simultaneously.
Disco revenue ≥ ¥500B (TSV wafer-thinning monopoly) — 6146.T — Disco annual revenue exceeds ¥500B reflecting structural demand from every HBM and CoWoS wafer requiring thinning and dicing. Disco/Accretech duopoly remains intact. Disco at ¥70,920 (+0.3% today, +11.7% since inception). HBM4 16-Hi stacks require more wafer thinning steps per stack, increasing Disco's revenue intensity per HBM unit. Jul 23 earnings will provide FY2026 guidance — key to watch for ¥500B trajectory.
Advantest revenue ≥ ¥1T (memory ATE supercycle) — 6857.T — Advantest revenue exceeds ¥1 trillion driven by HBM test capacity expansion and SoC ATE for AI accelerators. Memory ATE near-monopoly position. BULLISH: Advantest at ¥26,560 (+5.2% today, shares jumped as much as 14% on CNBC report citing AI chip boom). +1.6% since inception but strong momentum. The Advantest near-monopoly on HBM final test makes this the highest-conviction ATE play — every HBM stack must be tested, and stack count is growing exponentially with AI accelerator adoption.
