Through-Silicon Via (TSV) is the vertical copper interconnect that passes through silicon dies to enable 3D stacking — the foundational technology that makes HBM physically possible. The full TSV process flow adds ~19 materials-engineering steps on top of the ~700 steps for standard DRAM and spans deep silicon etching, oxide liner deposition, barrier and seed layer PVD, electrochemical copper fill, CMP, wafer thinning, and double-sided processing. Equipment-side concentrated at Applied Materials (TSV etch + drill-and-fill, ~75% process-step coverage), Lam Research (deep silicon etch, multi-year SK hynix deal), and Tokyo Electron. The wafer-thinning and dicing duopoly sits with Disco and Tokyo Seimitsu/Accretech.