TSMC's CoWoS (Chip-on-Wafer-on-Substrate) family and equivalents — the 2.5D and 3D packaging platforms that integrate logic dies with HBM stacks on a silicon or RDL interposer. Includes CoWoS-S, CoWoS-R, CoWoS-L (Local Silicon Interconnect with embedded bridges), and SoIC (System on Integrated Chips) 3D stacking. The binding capacity bottleneck for every leading-edge AI accelerator from NVIDIA H100/Blackwell/Rubin through AMD MI300/MI400 and hyperscaler custom silicon.