Nvidia's GPU roadmap after Blackwell — Vera Rubin (HBM4, Rubin CPX, the Groq 3 LPX pairing), Feynman — and the viral X napkin for a 'Big Boss' architecture: LPDDR6, no HBM, no CoWoS, cheaper tokens. The read-through for $NVDA, $MU, $ALAB, $AVGO, $QCOM.
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Nvidia's ($NVDA) GPU roadmap currently reads Blackwell (2024) → Vera Rubin (2026) → Feynman (2028): TSMC 4NP silicon to 3nm chiplets, HBM3e to HBM4, NVLink 5's 1.8 TB/s doubling to NVLink 6's 3.6 TB/s, each generation named after a scientist who changed physics. This guide covers that roadmap — and a viral X thread proposing the architecture that should come next: designed interconnect-first, fed by phone memory, built on a boring old process node, and named Big Boss, after a guy from X who wants cheaper tokens.
The thread is a joke that contains a real argument, and the argument has real tickers attached. Nvidia Rubin ships this year with more of everything. The counter-thesis says "more of everything" is the wrong axis: for inference, the binding constraint is the interconnect, and once you design for the pipe instead of the chip, the chip that falls out is small, cheap, and HBM-free. Markets are already pricing pieces of that world, whether or not anyone ever tapes out a Big Boss.
👉 The pipe, as a trade: the companies that sell the interconnect layer — switch silicon, retimers, SerDes — sit in the Networking / Retimers basket: $AVGO, $MRVL, $ALAB, $CRDO, $ANET and friends, in one live view.
Nvidia names its architectures after scientists. Ampère founded electrodynamics, Grace Hopper invented the compiler, David Blackwell put game theory on a rigorous footing, Vera Rubin measured galaxy rotation curves and showed dark matter is real, Richard Feynman rebuilt quantum electrodynamics. The naming bar is high. Hold that thought.
The three generations that matter for the next two years:
Every step on that road makes the same bet — keep the model's weights in the most expensive memory ever manufactured, bonded as close to the compute as advanced packaging allows, and grow the package when you need more. The X thread's bet is the opposite one.
In early July 2026, an account called @0xBADB01E posted a long thread — quote-tweeting @jwt0625 and a SemiAnalysis piece on interconnects — arguing that the industry has the priority order backwards. Chips get the keynotes; interconnects decide the economics. His claim: "we are best served by designing our interconnect first and then working backwards towards the optimal chip architecture."
The thread then does exactly that, in public, on a napkin. What falls out is an inference machine with no HBM, no CoWoS, no leading-edge node, and — per the author's own summary — "mobile SoC level economics" (his phrasing was more enthusiastic). The Macroplane version of the joke writes itself: after Blackwell the statistician and Rubin the astronomer, the roadmap ends at Big Boss, named after a guy from X who wants cheaper tokens.
The napkin deserves to be taken seriously, because each step is a real constraint you can check.
Start from an ugly fact about inference. Autoregressive decode — the token-by-token generation phase — runs at under 20% of peak FLOPs on Blackwell, per the thread. All those reticle-sized dies spend most of each decode step waiting for weights to arrive from memory. This is the memory wall: bytes, not FLOPs, are the constraint.
The naive fix is more memory bandwidth, which is the roadmap Nvidia is already on (HBM3e → HBM4). The clever fix, the thread argues, is to feed the idle FLOPs by streaming weights over the interconnect from other chips' memory — disaggregated memory, rediscovered from first principles. One problem:
NVLink 5 carries 1.8 TB/s against 8 TB/s of local HBM. The pipe to your neighbor's memory is 4.4× thinner than the pipe to your own, and scale-out networking is another order of magnitude behind that. Relying on remote memory makes tokens slower, so nobody does it, so each GPU's 192 GB stays effectively private. Which yields the thread's lemma, the single most useful sentence in it: remote memory is only as fast as the interconnect that reaches it — so the pipe must be sized to the memory it feeds.
| Memory type | Bandwidth class | Link needed to pool it |
|---|---|---|
| SRAM | extreme | ~80 TB/s |
| HBM3e/HBM4 | ~8+ TB/s | 2+ TB/s |
| LPDDR5X/LPDDR6 | ~0.5–1 TB/s | a few hundred GB/s |
Read the last row twice. Pooling HBM needs a link nobody can build economically. Pooling phone memory needs PCIe.
The thread is fair on this point: NVLink is high-bandwidth and high-latency because Nvidia optimized for training. Training is dominated by collective operations on enormous tensors — a few microseconds of latency on a giant all-reduce disappears into the transfer time, so you happily pay 224G PAM4 signalling plus forward-error-correction overhead to maximize bandwidth. And GPUs hide latency with occupancy anyway. A latency-tolerant fabric for a latency-tolerant chip: coherent design, for training.
Inference inverts it. Decode moves small tensors constantly — 8 KB activations, not 100 MB gradients — and every microsecond of link latency sits directly on the critical path of every token. For that workload you want the opposite fabric: lower bandwidth is fine, but latency must approach memory-access latency. LPDDR reads cost ~100 ns, about the same as HBM. A ~30 ns link makes remote LPDDR nearly indistinguishable from local memory. At which point, why buy the expensive memory at all?
Here is the napkin, reproduced as published (none of this is a shipping product; that is rather the point):
Scale both to a rack and compare:
| GB200 NVL72 (shipping) | "Big Boss" rack (napkin) | |
|---|---|---|
| Compute | 72 × B200 (+ 36 Grace CPUs) | 576 × 144 mm² N6 chips |
| Process node | TSMC 4NP | TSMC N6 |
| Memory | 13.8 TB HBM3e (+ ~17 TB Grace LPDDR5X) | 110 TB LPDDR6 |
| Aggregate memory bandwidth | ~576 TB/s | ~576 TB/s |
| Scale-up link | NVLink 5, 1.8 TB/s per GPU, switched | PCIe 5.0 full mesh, ~224 GB/s any-to-any |
| Link latency | microsecond-class through switches | ~30 ns claimed |
| Rack power | ~120–130 kW | ~104 kW |
| Advanced packaging | CoWoS throughout | none |
| Leading-edge silicon | yes | none |
| Can you buy one | yes, for a few million dollars | no, it's a tweet |
Same aggregate bandwidth by construction — which the thread reads as same tokens/sec, a leap the counter-napkin below will tax — with ~8× the memory pool, ~20% better tokens per watt and 4.5× less compute silicon, claims the thread says only get stronger as reasoning chains and agentic workloads put all-reduce latency on every token's critical path. Note the goalposts, too: the comparison is against Blackwell, and the Vera Rubin NVL72 raises the HBM side to 1,580 TB/s per rack.
One footnote worth savoring: the NVL72 already ships with ~17 TB of LPDDR5X bolted to its Grace CPUs — more capacity than its entire HBM pool — and the Vera generation carries 54 TB of it. It just sits behind ~0.5 TB/s per CPU, at the wrong end of the ladder above. The memory is there. The pipe isn't.
Dismissing this as napkin-ware was easier a year ago. Put the industry's announcements in order and the tell becomes a trend line:
The software went mainstream first. Splitting prefill from decode and running them on different hardware is not a fringe idea anymore: Microsoft's Splitwise and DistServe formalized the two-phase split in 2023–24, and Nvidia's own Dynamo framework plus TensorRT-LLM run disaggregated inference in production, routing phases to different pools and shuttling KV cache between them.
None of these is the full mesh-of-cheap-chips design. All of them are the same first principle: match the memory tier to the inference phase, and stop paying HBM prices for bytes that don't need HBM latency-bandwidth.
In the spirit of the genre, the counter-napkin:
You don't need Big Boss to tape out for the argument to pay. The thread's core claim — the pipe, not the chip, decides the economics — is already visible in two years of market action, and Macroplane tracks the whole layer.
The interconnect layer itself. If inference architectures keep disaggregating (prefill vs decode, memory tiers, weight streaming), every design needs more links, more retimers, more SerDes, more switch silicon. That is Broadcom ($AVGO) and Marvell ($MRVL) in switch and interconnect silicon, Astera Labs ($ALAB) — whose entire business is making PCIe go farther, and whose product line is what a Big Boss node would actually be wired with — Credo ($CRDO) in SerDes and active electrical cables, and Arista ($ANET) at the fabric-system level. The Networking / Retimers basket is up ~265% on an equal-weight basis over the trailing two years:
The photonics escape hatch. The napkin uses copper PCIe because its mesh is eight chips in one chassis. The moment low-latency links need to span a rack or a row, the physics hands the problem to optics — co-packaged optics, linear pluggable optics, optical circuit switching. That thesis lives in the Silicon Photonics & Optical Interconnects trend and the Photonics / CPO basket, and we mapped the component chain in the co-packaged optics deep dive.
The open-standard pipe. The same conclusion is being drawn outside Nvidia's walls, which makes "the pipe is the product" bigger than any one vendor. UALink is an open scale-up fabric — 200G per lane, up to 1,024 accelerators in a pod — built so the non-NVLink accelerator camp can wire racks the same way. CXL memory pooling turns "someone else's DRAM at 200–500 ns" into a shipping product for KV-cache tiers, with pools scaling toward 100 TiB per cluster. Both standards need the same physical layer: retimers, controllers, switch silicon. Astera Labs ($ALAB) already sells CXL memory-connectivity controllers alongside its PCIe retimers — it gets paid whichever fabric wins.
Memory: heads they win, tails they win. An HBM future pays Micron ($MU), SK Hynix and Samsung premium margins on stacked dies (the High Bandwidth Memory trend). An LPDDR future pays the same three companies for 8× the capacity per rack at commodity margins — into a market where UBS already sizes memory at $786B this year. The Memory Supercycle basket covers the complex; the Micron deep dive and the CXMT read-through cover the cycle.
The quiet losers. A world with less HBM per token is a world with less CoWoS, fewer TCB bonders, and less leading-edge logic per token — the HBM / Packaging basket and the Advanced Semiconductor Packaging trend are the exposure to watch, though Rubin's CoWoS demand makes this a 2028+ question, not a 2026 one. TSMC ($TSM) is fine in every branch: 4NP, N3, and the napkin's beloved N6 are all its nodes, and N6 capacity is long-since depreciated. Custom inference silicon of any flavor also lands in the same Custom Silicon basket — $NVDA, $AMD, $QCOM, $CBRS and the ASIC design chain.
What is Nvidia Rubin? Rubin is Nvidia's GPU architecture succeeding Blackwell, shipping from 2026, named after astronomer Vera Rubin. It moves to a chiplet design on a 3nm-class TSMC process, introduces HBM4 (pooling up to 20.7 TB per rack), doubles scale-up interconnect to 3.6 TB/s per GPU with NVLink 6, and adds Rubin CPX, a companion processor for long-context inference.
What comes after Rubin on Nvidia's roadmap? Feynman, announced at GTC 2025 and slated for around 2028, named after physicist Richard Feynman. Nvidia has published few specifics. "Big Boss" comes after that, according to one guy on X. Nvidia has not commented, because it is a joke.
What is Rubin CPX? A Rubin-family processor specialized for the context/prefill phase of reasoning models — the phase that reads long inputs. It carries 128 GB of GDDR7 instead of HBM and delivers up to 30 petaflops of NVFP4, per Nvidia's September 2025 announcement — the clearest early sign that even Nvidia segments inference by memory tier rather than putting HBM behind every token.
What is NVIDIA Groq 3 LPX? The inference companion Nvidia now pairs with Vera Rubin NVL72: a rack of 256 SRAM-based LPU accelerators built on Groq's technology. Per Nvidia's product page, an LPX rack carries 128 GB of SRAM at 40 PB/s plus 12 TB of DDR5, with 640 TB/s of scale-up bandwidth, and Nvidia claims up to 35x higher throughput per megawatt and one-tenth the cost per million tokens for the pairing on trillion-parameter models. It is the strongest evidence yet that different inference phases want different memory tiers behind a very fast pipe.
Is "Big Boss" a real chip? No. It is a design exercise from an X thread by @0xBADB01E: LPDDR6 for capacity, ~280 TF of FP4 on TSMC N6, and a full-mesh PCIe 5.0 fabric with ~30 ns links, yielding a rack that matches a GB200 NVL72's aggregate memory bandwidth with 8× the memory and no HBM or CoWoS. Nobody manufactures it. Its ideas — memory-tier matching, latency-first interconnects, disaggregated inference — are all live in shipping and announced products: Rubin CPX, the Groq 3 LPX pairing, Qualcomm's AI200/AI250, Intel's Crescent Island.
What is the memory wall in AI inference? During autoregressive decode, a GPU must stream model weights (and KV cache) from memory for every generated token, so throughput is bounded by memory bandwidth rather than compute — utilization on Blackwell-class hardware can sit under 20% of peak FLOPs. Fixes include faster memory (HBM4), smarter batching, quantization (FP4), and the architectural routes discussed here.
Which stocks benefit if the interconnect becomes the bottleneck? The interconnect layer itself ($AVGO, $MRVL, $ALAB, $CRDO, $ANET — the Networking / Retimers basket), optics as links leave the chassis (the Photonics / CPO basket), and the memory oligopoly in every scenario ($MU, SK Hynix, Samsung). This is research and education, not investment advice — napkin math least of all.