High-bandwidth memory is the memory-bandwidth substrate of the AI compute stack — 3D-stacked DRAM dies bonded through TSVs onto a logic base and co-packaged with accelerator silicon over silicon interposers. Demand is set by the shipment rate of NVIDIA, AMD, and hyperscaler ASICs, where HBM capacity per accelerator continues to grow with each generation and typically sells out on multi-year LTAs. Supply is an effective oligopoly (SK Hynix, Samsung, Micron), with HBM3E ramping through 2026 and HBM4 in qualification; the binding constraints are advanced-DRAM wafer capacity, base-die logic supply from foundries, and back-end capacity for TSV etch, hybrid bonding, and known-good-die test. Equipment beneficiaries include Advantest and Teradyne (memory test), Disco (grinding/dicing), TEL and AMAT (etch/deposition), and BESI (hybrid bonding). Wafer, photoresist, and specialty-chemical suppliers upstream (Shin-Etsu, SUMCO) capture the raw-materials pull-through.
Browse all macro trends · Product categories · Industries · Companies