Equipment and materials used to fabricate semiconductors — wafer fabrication, inspection and metrology tools, cleanroom equipment, lithography photomasks, electronic materials and process chemicals (including CMP slurries and pads), silicon wafers, advanced packaging (including hybrid bonding and through-silicon via processes) and OSAT, semiconductor test equipment and probe cards, EDA software, foundry and fab services, and compound semiconductor epitaxy.
Product categories in Semiconductor Equipment & Materials
Cleanroom Equipment — Cleanroom systems, filtration, and contamination control
CMP Slurries & Pads — Materials for chemical mechanical planarization to polish wafers flat.
Compound Semiconductor Epitaxy — Epitaxial wafer manufacturing for compound semiconductors — III-V materials (GaAs, GaN, InP) and IV-IV SiC — grown by MOCVD, MBE, or CVD onto native or engineered substrates. Serves wireless RF (GaAs/GaN HEMTs, PAs, filters), optoelectronics (VCSELs, DFB lasers, photodiodes, LEDs), power electronics (SiC and GaN switches for EVs, chargers, PV inverters, datacenter PSUs), and sensing (LiDAR, imaging).
EDA Software — Electronic design automation tools for chip design and verification
Electronic Materials — Substrates, sputtering targets, bonding wires for electronics
Foundry / Fab Services — Contract semiconductor manufacturing — wafer fabrication for fabless and partially-fabless customers, spanning leading-edge logic, mature-node analog/mixed-signal, RF, and specialty processes (BCD, BiCMOS, SiC, SOI).
Hybrid Bonding Equipment — Direct copper-to-copper bonding without solder microbumps — the next-generation stacking interconnect for HBM5+ and high-end logic-on-logic 3D integration. Enables sub-1µm pitches versus 25-40µm for thermocompression bonding (TCB), allowing 20-Hi+ HBM stacks and TSMC SoIC. Wafer-to-wafer (W2W) hybrid bonding is expected to become mainstream in the HBM5 generation (~2028-2029); die-to-wafer (D2W) for higher mix. Equipment is concentrated at BE Semiconductor (BESI), ASMPT, and Applied Materials, with EV Group and SUSS Microtec on the prep side.
OSAT — Outsourced semiconductor assembly and test services
Silicon Wafers — Raw silicon wafer manufacturing and supply
Through-Silicon Via (TSV) Process — Through-Silicon Via (TSV) is the vertical copper interconnect that passes through silicon dies to enable 3D stacking — the foundational technology that makes HBM physically possible. The full TSV process flow adds ~19 materials-engineering steps on top of the ~700 steps for standard DRAM and spans deep silicon etching, oxide liner deposition, barrier and seed layer PVD, electrochemical copper fill, CMP, wafer thinning, and double-sided processing. Equipment-side concentrated at Applied Materials (TSV etch + drill-and-fill, ~75% process-step coverage), Lam Research (deep silicon etch, multi-year SK hynix deal), and Tokyo Electron. The wafer-thinning and dicing duopoly sits with Disco and Tokyo Seimitsu/Accretech.
