AI supply-chain thesis — mapping bottlenecks, focus companies, and supply-chain exposure for investors.
**Bottleneck theme:** Lithography & Fab Tools **Focus:** $LRCX — LAM RESEARCH CORP Lam Research is the etch monopoly. For the most demanding etch steps in modern fabs — high-aspect-ratio TSV (through-silicon via) etch in HBM, 3D NAND staircase / channel-hole etch, advanced-packaging via formation, and gate-all-around fin-removal — Lam holds 80%+ share and is functionally sole-source. Every HBM stack drives roughly 4-6x more etch tool time than a planar DRAM die, so the HBM3E → HBM4 → HBM4E roadmap maps directly to per-wafer Lam revenue growth. Add 3D NAND moving from ~200 layers to ~400 layers (each layer is more etch passes) and the secular content tailwind is unambiguous. Lam's secondary lever is advanced packaging — CoWoS, hybrid-bonding via formation, and the metallization steps around each. The bear case is China NAND/DRAM exposure (export-control risk) and lumpy memory CapEx cycles. But the structural content-per-wafer story compounds: each new memory generation adds more etch passes, and Lam's installed-base service revenue grows with the world's wafer-start count regardless of cycle. Pair-trade or peer comp candidates: $AMAT, $TER, $ASML.
**Bottleneck theme:** Lithography & Fab Tools **Focus:** $LRCX — LAM RESEARCH CORP Lam Research is the etch monopoly. For the most demanding etch steps in modern fabs — high-aspect-ratio TSV (through-silicon via) etch in HBM, 3D NAND staircase / channel-hole etch, advanced-packaging via formation, and gate-all-around fin-removal — Lam holds 80%+ share and is functionally sole-source. Every HBM stack drives roughly 4-6x more etch tool time than a planar DRAM die, so the HBM3E → HBM4 → HBM4E roadmap maps directly to per-wafer Lam revenue growth. Add 3D NAND moving from ~200 layers to ~400 layers (each layer is more etch passes) and the secular content tailwind is unambiguous. Lam's secondary lever is advanced packaging — CoWoS, hybrid-bonding via formation, and the metallization steps around each. The bear case is China NAND/DRAM exposure (export-control risk) and lumpy memory CapEx cycles. But the structural content-per-wafer story compounds: each new memory generation adds more etch passes, and Lam's installed-base service revenue grows with the world's wafer-start count regardless of cycle. Pair-trade or peer comp candidates: $AMAT, $TER, $ASML.
The Etch monopoly for HBM TSV + 3D NAND staircase + advanced packaging thesis on Macroplane focuses on LAM RESEARCH CORP (LRCX).
It covers Etch Equipment, Memory Supercycle, Foundry / Fab Services, HBM, NAND Flash, Advanced Packaging, AI Training Accelerators, Hyperscalers.
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