ZeroFlap AECs are de-facto AI scale-up cabling standard

Focus companies in this thesis (1)

• Credo Technology Group Holding Ltd (CRDO)

Supply-chain categories covered

• Networking / Retimers — Investment-thesis bucket from bottlenecks.app: Networking / Retimers
• SerDes IP — Serializer/Deserializer intellectual property cores for high-speed data links in AI networking chips.
• ASICs — Application-specific integrated circuits (AI accelerators, crypto miners, custom SoCs)
• Network Switches & Routers — Data center and enterprise networking equipment
• AI GPUs — Compute accelerators and GPUs powering AI training, inference, and large language models.
• Hyperscalers — Major cloud operators (AWS, Azure, GCP, Meta, Oracle, Alibaba, Tencent, Baidu, Naver) and tier-2 / neocloud providers (DigitalOcean, OVHcloud, Rackspace, Kingsoft) tracked as a demand signal across multiple theses (photonics, HBM, AI accelerators, power, cooling). Excludes SaaS apps, telcos, REITs, and IT services firms.

Thesis milestones & bottleneck markers

• $CRDO gross margin expansion — CRDO
• $CRDO revenue > $1B — CRDO
• AI networking TAM growth — Ethernet AI scale-up market expansion

Related baskets

• Networking / Retimers

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Frequently asked questions

What is the ZeroFlap AECs are de-facto AI scale-up cabling standard thesis about?

**Bottleneck theme:** Networking / Retimers **Focus:** $CRDO — Credo Technology Group Holding Ltd Credo's ZeroFlap AECs (active electrical cables) have become the de-facto AI scale-up cabling standard. Inside an AI rack, the GPU-to-GPU and GPU-to-switch links need higher bandwidth and lower latency than passive copper at distance, but optical is overkill for short reach — AECs hit the sweet spot, replacing ~40% of optical sockets that would otherwise have shipped at 800G and 1.6T inside racks. NVIDIA NVL72/NVL576 and the Ultra Ethernet Consortium specs all reference AECs for short-reach scale-up, and Credo has been the volume vendor of choice through hyperscaler and OEM (Arista, Celestica) channels. The investment case is product cycle (AECs replace optical and passive copper at attractive ASPs) plus volume socket expansion as 1.6T scale-up fabrics deploy in 2026-2027. The bear case is incumbent pushback (Marvell, Broadcom, Astera all want this socket), short product-cycle risk (AEC may be a transition technology before CPO at 3.2T+), and customer concentration in a small number of hyperscaler programs. Pair with $ALAB (PCIe retimers + Scorpio scale-up) and $MRVL (DSP retimer competitor).

Which companies does the ZeroFlap AECs are de-facto AI scale-up cabling standard thesis focus on?

The ZeroFlap AECs are de-facto AI scale-up cabling standard thesis on Macroplane focuses on Credo Technology Group Holding Ltd (CRDO).

Which supply-chain categories does the ZeroFlap AECs are de-facto AI scale-up cabling standard thesis cover?

It covers Networking / Retimers, SerDes IP, ASICs, Network Switches & Routers, AI GPUs, Hyperscalers.